Assessment of LS-DYNA Scalability Performance on Cray XD1

Technologists worldwide have now recognized that CAE (Computer Aided Engineering) offers an unprecedented opportunity to revolutionize product development. Today, CAE promises not only increased productivity but also faster time-to-market, lower warranty costs and above all, products that are safer, outperform and work better. With the broad acceptance of the MPI based implementation of LS-DYNA, the manufacturing industry is pushing the limits of scalability as they scramble to meet stringent product design cycle constraints. Microprocessor based cluster systems are increasingly being deployed for production workloads. But, the scalability and system efficiency can be very poor on such systems. The industry goal to reduce time-to-market can be met only if the system has a balanced architecture and the interconnect technology is able to deliver sustained performance for actual applications. In this study, an in-depth analysis will be performed to assess the performance of LS-DYNA on Cray’s XD1 system. A correlation between the hardware features of Cray XD1 and the attributes of LS-DYNA will be made. Various phases involved in a typical crash simulation, such as - initialization, element processing, contact and rigid bodies calculations will be analyzed. An MPI profiling tool will be used to monitor the MPI performance in the context of computation, communication and synchronization aspects of LS-DYNA. The communication patterns and message sizes will be studied for variety of standard benchmarks ( www.topcrunch.org ). The role of Cray XD1’s balanced architecture and the HHTUTU UUTTHH high speed interconnect technology will be presented in the specific context of LS-DYNA and production workloads. Performance results of LS-DYNA on Cray XD1 will be highlighted that truly demonstrate “Application efficiency at scale”.